The present invention relates to logic circuits or associated devices comprising field-effect transistors and, more specifically, to logic circuits comprising vertical transport field effect transistors for reducing the footprint of logic circuits.
Digital logic circuits, also referred to as logic gates, are the building blocks of digital electronics and integrated circuits. A commonly used digital logic circuit is an inverter. Other fundamental logic circuits can include, among others, NAND and NOR circuits, wherein an accompanying number, such as the “3” in NAND3, can indicate the number of active gates in the logic circuit. Each of these logic circuits can perform a different logical operation. In a standard cell library, a number of transistors can be connected either in series and/or in parallel to perform NAND, NOR and other complex Boolean functions.
Complementary metal oxide semiconductor (CMOS) technology is currently the dominant technology for the manufacture of inverters and other logic gates used in digital integrated circuits, including microprocessors, microcontrollers, or static random access memory (SRAM). The word “complementary” refers to the fact that a typical CMOS circuit may use complementary pairs of hole-type (positive) and electron-type (negative) FETs (field effect transistors), i.e., p-FETs and n-FETs, respectively. The n-FET uses electrons as the current carriers in combination with n-doped source and drain junctions. The p-FET uses holes as the current carriers in combination with p-doped source and drain junctions. CMOS technology can offer low static power consumption and high noise immunity, when compared to other digital technologies.
An FET (also referred to as MOSFET) is a field effect transistor that can be used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a gate electrode. The gate electrode can comprise a conductive gate that is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
Vertical Transport FETs (VTFETs) are a promising alternative to standard lateral FET structures due to potential benefits, among others, in terms of reduced circuit footprint. In this type of structure, the current flow is perpendicular to a supporting wafer, unlike the lateral current flow in lateral FETs. A logic circuit comprising VTFETs can be referred to as a “vertical transport logic gate.”
In other words, VTFETs can potentially provide electronic devices comprising logic circuits with improved circuit density. Such logic circuits can be characterized by a lower-number CPP (cell gate pitch) versus comparable logic circuits comprising lateral FET layouts. Minimum wiring pitch can also be relevant for realizing denser vertical FET layouts.
Although VTFETs are a promising alternative to conventional lateral FET structures for use in logic circuits, a challenge has been the circuit and layout-level implications of employing VTFETs in integrated circuits.